The multiplication of two values is a common operation performed in arithmetic logic units. A conventional multiplier (e.g., a 16.times.6 multiplier) receives a 16-bit multiplicand and a 16-bit multiplier and generates a 32-bit product using a Wallace tree.
The multiplier requires input values of a fixed bit length of 16 bits each. In order to multiply values having other bit length (e.g., a 4.times.4 multiplication), the input values must be bit extended with additional bits having no additional information. For example, if a 4.times.4 operation is to be performed, the 4-bit input values must be extended to 16 bits before multiplication. The additional 12 bits of each input have no useful information resulting in the 32-bit product having 24 bits of useless information.
Furthermore, the current multiplier is limited in that it only performs multiplication in series, one multiplication per operation cycle.
Therefore, what is desired is a circuit and method which 1) increase the input bit size format flexibility of the multiplier thereby reducing input value bit extension, and 2) allow for several multiplications to be performed in parallel using a single multiplier.